Conventional computer systems include a processor coupled to a variety of memory devices, including read-only memories ("ROMs") which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory ("SRAM"). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors are currently available that operate at clock speeds of at least 200 megahertz. However, the remaining components of the computer system, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 200 MHz clock frequency may be mounted on a motherboard having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 200 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories ("DRAMs"). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories ("SDRAMs") have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, typical SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as "SyncLink." In the SyncLink architecture, the system memory may be coupled to the processor directly through the processor bus. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that is coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the SyncLink architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled to three packetized dynamic random access memory or SyncLink DRAM ("SLDRAM") devices 16a-16c. The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through a bus bridge 22 and an expansion bus 24, such as an industry standard architecture ("ISA") bus or a peripheral component interconnect ("PCI") bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives, floppy disk drives, tape cassettes, and compact-disc read-only memory (CDROM) drives.
In operation, the processor 12 communicates with the memory devices 16a-16c via the processor bus 14 by sending the memory devices 16a-16c command packets that contain both control and address information. Data is coupled between the processor 12 and the memory devices 16a-16c, through a data bus portion of the processor bus 14. Although all the memory devices 16a-16c are coupled to the same conductors of the processor bus 14, only one memory device 16a-16c at a time reads or writes data, thus avoiding bus contention on the processor bus 14. Bus contention is avoided by each of the memory devices 16a-16c and the bus bridge 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines which have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16a-16c also receive a master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device 16, and a FLAG signal signifying the start of a command packet.
The memory devices 16 are shown in block diagram form in FIG. 2. Each of the memory devices 16 includes a clock divider and delay circuit 40 that receives a master clock signal 42 and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16. The memory device 16 also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock CLK signal, a command packet CD on a command bus 50, and a FLAG signal on line 52. As explained above, the command packet contains control and address information for each memory transfer, and the FLAG signal identifies the start of a command packet which may include more than one 10-bit packet word. In fact, a command packet is generally in the form of a sequence of 10-bit packet words on the 10-bit command bus 50. The command buffer 46 receives the command packet from the bus 50, and compares at least a portion of the command packet to identifying data from an identification ID register 56 to determine if the command packet is directed to the memory device 16a or some other memory device 16b, c. If the command buffer determines that the command is directed to the memory device 16a, it then provides a command word to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16a during a memory transfer.
The address capture circuit 48 also receives the command words from the command bus 50 and outputs a 20-bit address corresponding to the address information in the command. The address information is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM 16a shown in FIG. 2 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-80h. After a memory read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-80h are being accessed. Each of the memory banks 80a-80h receives a row address from a respective row latch/decoder/driver 82a-82h. All of the row latch/decoder/drivers 82a-82h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. Bank control logic 94 activates only one of the row latch/decoder/drivers 82a-82h as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100 which, in turn, supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-80h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-80h through the sense amplifiers 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 receiving and storing data from the I/O gating circuit 102. In the memory device 16a shown in FIG. 2, 64 bits of data are applied to and stored in the read latch 120. The read latch then provides four 16-bit data words to a multiplexer 122. The multiplexer 122 sequentially applies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked through the FIFO buffer 124 by a read clock signal LATCHR generated from an internal clock by a programmable delay circuit 126. The FIFO buffer 124 sequentially applies the 16-bit words to a driver circuit 128 which, in turn, applies the 16-bit data words to a data bus 130 forming part of the processor bus 14.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit words from the data bus 130 to four input registers 142, each of which is selectively enabled by a write clock signal LATCHW from a clock generator circuit 144. Thus, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by the write clock signal LATCHW from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-80h through the I/O gating circuit 102 and the sense amplifier 104.
As mentioned above, an important goal of the SyncLink architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. However, the operating rate of a packetized DRAM, including the packetized DRAM shown in FIG. 2, is limited by the time required to process command packets applied to the memory device 16a, the time required to generate control signals and the time required to read and write data to the banks 80a-h. More specifically, not only must the command packets be received and stored, but they must also be decoded and used to generate a wide variety of control signals. The control signals must then be communicated to the various circuitry for accessing the banks 80a-h. However, in order for the memory device 16a to operate at a very high speed, the command packets must be applied to the memory device 16a at a correspondingly high speed.
As the memory device receives and processes command packets at high speeds, the I/O gating circuit 102, sense amplifiers 104, and other circuitry for reading and writing to the memory banks 80a-80h produce internal command signals at very high speeds. These high speed command signals must be delivered to the circuitry associated with each of the eight banks 80a-80h. For example, command signals such as precharge and equilibrate are transmitted to the row latch/decoder/drivers 82a-82h from the decoder and sequencer 60. Delivery of all of the command signals to the eight banks 80a-80h can require several sets of signal lines, each extending from the command decoder and sequencer 60 to each of the latch/decoder/drivers 82a-82h associated with each of the eight memory banks 80a-80h. Each of the lines consume valuable area on a substrate and complicate routing of signal lines.
Additionally, the internal control signals require time to propagate from the command sequencer and decoder 60 to the various circuitry for accessing the banks 80a-h. Routing differences between the bank control logic 94 and the latch/decoder/drivers 82a-82h can therefore cause differences in the times at which the command signals reach the latch/decoder/drivers 82a-82h. These differences in arrival times can become significant at high speeds of operation and eventually limit the operating speed of the packetized DRAM.